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Extra resources for Computer Safety, Reliability, and Security: 33rd International Conference, SAFECOMP 2014, Florence, Italy, September 10-12, 2014. Proceedings
Node DMI Core C. c. Node voter Core C. c. Node voter Processor Node Processor C. c. Node EVC C. c. Node EVC Comm. channel Node EVC Fig. 3. SUT: Railway signaling system modeled at PSM level nodes containing a single-core processor, whereas the each EVC node contains a dual-core processor. The ﬁrst core of the processor is the host for the odometry, mode-control and emergency-brake-system jobs, whereas the service-brake system job is hosted on the second core. We design the functions with SCADE and we generate C code automatically using the KCG tool.
As a conclusion, we state that the algorithm has shown to be specially sensitive to faults in the accelerometer, so future work could focus on the improvement of this fact. 2 Platform Speciﬁc Model The PSM of the system introduces redundancy in order to tolerate hardware related faults. A TMR architecture has been chosen in order to guarantee the availability of the system even in the presence of faults. As stated before, the voting algorithm should be able to identify any failure in the replicated nodes.
24 H. Schirmeier, C. Borchert, and O. Spinczyk Table 1. Information recorded for every dynamic def or use instruction executed during the golden run of each benchmark. , in CPU cycles) benchmark_id An ID uniquely identifying each benchmark The bitwise AND of an – initially randomly chosen – projection vector and each state vector yields a vector uniquely identifying the similarity class each def/use class belongs to. The example projection function from Sect. 1 – preserving only the components EIP, ESP, EBP, and the higher-order bits of EDX and EAX – can directly be encoded by setting the corresponding bits in this vector.